| 摘要 |
Departure of a logic signal from the ranges of signal values corresponding to defined logic levels is monitored by comparing the logic signal with the boundary values of these ranges. Provided the logic signal between transitions is below the lower threshold (14) or above the upper threshold (12), a NOR gate (16) and a D-type bistable circuit (18) open an AND gate (22) to enable a counter (24) to count 10 MHz clock pulses. If the logic signal is between the thresholds, the AND gate disables the counter. The four most significant digits of the total number of clock pulses actually counted after 1,000,000 have been supplied is displayed, giving an indication of the percentage of time for which the logic signal has a value corresponding to a defined logic level. As an alternative, the output signal of the NOR gate (16) can be inverted (26) and supplied to a moving-coil or digital voltmeter (30). |
