| 摘要 |
A method and apparatus for converting between analog signals and corresponding digital signals that is accurate relative to the actual value of the input signal, and not relative to the upper limit on the analog input signal. The method and apparatus are disclosed in terms of a serial-feed-back A/D converter that performs an A/D conversion through a plurality of cycles equal in number to the number of bits in the digital output word. In each cycle a comparison voltage is tested to determine if the bit output for the cycle is high or low. The comparison voltage is the amplified difference of the comparison voltage for the preceding cycle and another reference signal. The scale factor for the amplification of the difference between the two signals is one value if the bit value for the preceding cycle was high, and another complementary value if the bit value for the preceding cycle is low. The companion method and apparatus for converting a non-binary digital signal into a corresponding analog signal is also disclosed. |
