发明名称 PRIORITY CONTROL SYSTEM
摘要 PURPOSE:To change the priority of access, by changing the interruption priority to each processing processor specified according to the state of data processing progress. CONSTITUTION:When a managing processor 16 detects that the processing state of the 2nd processor 18 is behind than that of the 1st processor 17, the priority definning and selection signal set to a selection register 21 is set to a block 23-1 selection signal of a sub-memory 23. The priority is changed so that the 2nd processor 18 can access a main memory unit 2 with the highest priority. Thus, the processing speed in the 2nd processor 18 can be improved.
申请公布号 JPS5730049(A) 申请公布日期 1982.02.18
申请号 JP19800104585 申请日期 1980.07.30
申请人 FUJITSU LTD 发明人 YAMAZAKI ISAO;HANATANI KIYOKAZU;MATSUKAWA KATSUHIRO
分类号 G06F12/00;G06F9/48;G06F15/16;G06F15/177 主分类号 G06F12/00
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