发明名称 SUBSCANNING SPEED CONTROLLER FOR FACSIMILE
摘要 PURPOSE:To quickly and suitably perform the matching between the amount of production of a video signal and a transmission speed, by controlling the subscanning speed in response to the amount of storage of a buffer mimory. CONSTITUTION:A subscanning speed controller consists of a buffer memory 1, memory amount discriminating circuit 2, up/down counter 3, speed conversion read only memory 4, frequency dividing counter 5, and motor drive circuit 6. The buffer memory 1 stores a coded video signal and the memory content is transmitted to a transmission line with a transmitter. The data storage amount of the buffer memory 1 is discriminated at a memory amount discrimination circuit 2, and the signal according to the result of discrimination is given to the motor drive circuit 6 via the up/down counter 3, speed conversion read only memory 4 and the frequency dividing counter 5 for the control of subscanning speed.
申请公布号 JPS5728471(A) 申请公布日期 1982.02.16
申请号 JP19800103476 申请日期 1980.07.28
申请人 NIPPON ELECTRIC CO 发明人 TOMITA YASUHARU;MITSUOKA TAKASHI
分类号 H04N1/17 主分类号 H04N1/17
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