发明名称 ACCUMULATION INSTRUCTION PROCESSING SYSTEM
摘要 PURPOSE:To facilitate accumulation control by increasing the number of data, by adding data, when the number of data is less than that of arithmetic stages, as many as the deficient number. CONSTITUTION:A gate 12 turns on and off an input bus for the transfer of input data, and a gate 13 also turns on and off an input 0 transferred from a 0 generator 6. A control part 14 exercises on-off control over gates 8-10, and also controls preshifting circuits 1 and 2, an arithmetic circuit 3, and a host shifting circuit 4. In an initial cycle display counter 15, the number of arithmetic stages of an arithmetic processing part is set initially, and in a vector-length counter 16, the number of data to be accumulated is set initially. Then, 0 detectors 17 and 18, when the contents of conters 15 and 16 go down to 0s, detect those and generate outputs.
申请公布号 JPS5727360(A) 申请公布日期 1982.02.13
申请号 JP19800102052 申请日期 1980.07.25
申请人 FUJITSU LTD 发明人 MOGI MASANORI
分类号 G06F17/10;G06F7/50;G06F17/16 主分类号 G06F17/10
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