| 摘要 |
1. A method of producing an arrangement for reducing the sensitivity to radiation of integrated circuit MOS memory cells, in which a flip-flop is in each case provided as a memory element, the flip-flop nodes of which are connected by way of polysilicon load resistances to the supply voltage terminal, and in which the radiation sensitivity is reduced by increasing the node capacitances (CA , CB ) by implantation into the substrate beneath one of the diffusion zones (n**+ ) of a selector transistor (AT) assigned to the memory cell in question, wherein field oxide zones are produced in a first group of process steps, whereupon the thin gate oxide, into which holes are etched for the production of contacts between the polysilicon (which is to be applied subsequently) and the monocrystalline silicon, is applied over the entire surface, characterised in that, prior to the deposition of the required polysilicon areas and after contact-etching to increase the node capacitances (CA , CB ) by implantation into the substrate, an intermediate process step is carried out in which the remaining SiO2 areas are used as an implantation mask. |
