INTEGRATED SEMICONDUCTOR CHARGE STORAGE MEMORY

摘要

The merged charge memory system has an accessing arrangement. Each of the word lines of the memory array is divided into a number of segments with cells associated only with a selected one or a portion of the segments being coupled at any particular time to bit driving and sensing devices. Thus, only relatively few sense amplifiers compared with the number of bits per word of the array are required to handle all of the cells of the array. The flow of charges from charge source is released only to the cells of the selected word segment or segments which are simultaneously coupled to bit driving and sensing devices via associated it/sense lines. -