发明名称 Input/output data processing system
摘要 An input/output processor architecture for providing an interface between peripheral subsystems and a generalized data processor. The interface processor enables data to be transferred between two address spaces (the generalized data processor address space and an external processor I/O address space) by mapping a portion of the I/O address space into a portion of the GDP address space. This mapping facility provides the peripheral subsystem with a "window" into the associated GDP subsystem. It accepts addresses within a certain subrange, or subranges, and translates them into references into one or more GDP data segments. A function-request facility provides a functional capability over certain objects within the GDP address space. The two facilities provide software on an external processor with a window into the address space of the GDP that enables the software, via the function request means, to send messages to and receive messages from the GDP and to manipulate an environment provided for the external processor within its address space.
申请公布号 US4315310(A) 申请公布日期 1982.02.09
申请号 US19790079991 申请日期 1979.09.28
申请人 INTEL CORPORATION 发明人 BAYLISS, JOHN A.;COX, GEORGE W.;FORBES, BERT E.;KAHN, KEVIN C.
分类号 G06F12/02;G06F13/12;G06F13/42;G06F15/16;G06F15/177;(IPC1-7):G06F3/00 主分类号 G06F12/02
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