发明名称 BUS CONTROL SYSTEM
摘要 PURPOSE:To prevent an overall function stop of a system, by providing a means for rejecting the flow-in of an electric power supply from other CPU block in case when a self-CPU block has been disconnected from an electric power supply, on an interface, in a composite computer system. CONSTITUTION:CPU block 1A-1C constituting a composite computer system are provided with interfaces 5A-5C for communication and control. These interfaces 5A-5C are provided with not only a function for preventing the flow-in of an electric power supply from other CPU block through a system bus 3 or a control line 4 in a CPU block which has been disconnected from an electric power supply, but also a function by which the right of using of a system bus 3 is controlled without a hitch, therefore, even when disconnection of an electric power supply occurs in one CPU block, a function of other CPU blocks is performed normally.
申请公布号 JPS5725059(A) 申请公布日期 1982.02.09
申请号 JP19800098689 申请日期 1980.07.21
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 MAZAKI TOSHIO
分类号 H02J1/00;G06F1/26;G06F1/30;G06F3/00;G06F13/36;G06F15/16;G06F15/177;H04L5/22 主分类号 H02J1/00
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