| 摘要 |
<p>PURPOSE:To reduce the number of bits of a clocking counter along with an assurance of clocking accuracy by treating one part of the range of shutter time with a clocking counter and by using an RAM area of a micro-computer for other parts. CONSTITUTION:In a case where shutter time can be clocked by only 8 bits, the second FF4 is set and on a counter 11 the shutter time is preset. With start of travelling of an advance screen, the first FF2 is set with start of counting, and when the counter is overflowed a division circuit 41 is triggered, thus by the output a shutter time clocking termination signal is outputted from an AND gate 46. In a case where clocking of shutter time is impossible with 8 bits in the higher rank side of a code it is preset in an RAM area and the lower rank side code is preset in the counter. At this time the second FF is in a reset state, by overflow of the counter, control is transferred to a microcomputer, and after processing the second FF is set.</p> |
