发明名称 ADDRESS SETTING CIRCUIT OF MEMORY
摘要 PURPOSE:To facilitate an easy setting and alteration of an address and simplify the constitution of circuit, by securing a binary setting for the head of the address of a memory which is desired to be set at an address setting part. CONSTITUTION:The 2<10>-2<15> bits of an address bus 12 are all logic value O, and every terminal of (a)-(f) of an address setting part 14 is not earthed. In such case, side A of the input terminal of full adders 13A and 13B is logic value O each, and side B is logic value 1 respectively. Thus a carry input terminal CO is logic value 1, and the outputs of an adder 13 are all reduced to O and are supplied to a decoder 15. Accordingly the allotment of addresses are O-(8K-1) for memories 11-1-11-8 in case every terminal of the part 14 is not earthed. Then the outputs of the adder 13 are all reduced to logic O when only the terminal(d) of the part 14 is earthed and 2<13> bits of a bus 12 are reduced to logic 1. Thus the decoder 15 works.
申请公布号 JPS5724080(A) 申请公布日期 1982.02.08
申请号 JP19800098035 申请日期 1980.07.17
申请人 OLYMPUS OPTICAL CO 发明人 HIJIKATA KAZUO;NAKASHIMA YOSHIO
分类号 G06F12/06;G11C8/12 主分类号 G06F12/06
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