发明名称 MEMORY CELL
摘要 PURPOSE:To eliminate the change of potential between substata of a cell and increase the line selecting speed, by opening and closing a write/read control FET to carry out a selection of address plus a read/write action. CONSTITUTION:Read/write FET205 and 206 are connected to a writing circuit 215 and a sense amplifier 216 via write/read lines 209 and 210, and each gate is connected to a line address line transistor circuit 217 via a line 214. In the reading mode, a pulse 301 is applied to an address line 114, and read control pulses 304 and 307 are applied to terminals 209 and 210 each. Thus the change of current at the terminals 209 and 210 is detected by an amplifier 216, and the storage contents of a cell is read. While in the writing mode, a line address selection pulse 302 is applied to the line 114, and writing pulses 305 and 308 are applied to the terminals 209 and 210. Thus the potential of a terminal 211 is changed to a low level from a high level. At the same time, an FET202 is turned to eff from on and an FET201 is turned to on from off. Thus ''0'' for instance is written.
申请公布号 JPS5724093(A) 申请公布日期 1982.02.08
申请号 JP19800098577 申请日期 1980.07.18
申请人 NIPPON ELECTRIC CO 发明人 SUZUKI MASAO
分类号 G11C11/411;H01L27/10 主分类号 G11C11/411
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