发明名称 BUFFER MEMORY CONTROL SYSTEM
摘要 PURPOSE:To ensure a highly efficient repealing process of a buffer memory, by transmitting the write request address to the own processor when the main storage read request is detected for the own processor. CONSTITUTION:Address buffer registers ABR10 and 11 comprise plural registers each. The write addresses of processors B, C and D to a main storage are stored in the ABR10; and the write addresses of processors A, C and D to the main storage are stored in the ABR11 respectively. The addresses stored in the ABR10 and 11 are retained until the main storage read requests are produced from the processors A and B. And circuits 14 and 15 conduct by the outputs of OR circuits 12 and 13 when the request is produced. Then the address information is read out of the ABR10 and 11 to be transmitted to the corresponding processors A and B by the circuits 14 and 15 plus buffer repealing address information lines 24 and 25.
申请公布号 JPS5724088(A) 申请公布日期 1982.02.08
申请号 JP19800099671 申请日期 1980.07.21
申请人 FUJITSU LTD 发明人 KOGA SATOSHI
分类号 G06F12/08;G06F13/16 主分类号 G06F12/08
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