发明名称 REPEALING COTROL SYSTEM OF BUFFER MEMORY
摘要 PURPOSE:To realize a simple and effective repealing control of a buffer memory and increase the working efficiency of a processor, by installing plural buffer repealing address holding registers plun an address comparator. CONSTITUTION:A store address to a main memory is sent to the corresponding processor in the form of a buffer repealing address in order to secure a coincidence of contents between a main memory and a buffer memory. In this case, plural buffer repealing address holding registers AB1-AB4 plus an address comparator ADC are provided at the sending side of buffer repealing address. Then the store address belonging to the same block is prevented from being held in a plural number in each register AB by the comparator ADC. And the contents of the AB are sent successively to the corresponding to processor in an appropriate period.
申请公布号 JPS5724086(A) 申请公布日期 1982.02.08
申请号 JP19800097799 申请日期 1980.07.16
申请人 FUJITSU LTD 发明人 TAMURA HIROSHI
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项
地址