| 摘要 |
PURPOSE:To permit one processor to attain access without conflicting with other requesting origins, by giving a priority to only one of interruption requests generated simultaneously and by rejecting other interruption requests. CONSTITUTION:Once an interruption request pulse 5i is inputted to a circuit Si, an inhibiting gate 1 connecting with a signal line 11 indicating the state of an interruption priority acquisition bus 4 permits the pulse 5i on an interruption request line 12 to pass through it, and sets a flip-flop (FF) 2. As the FF2 is set, a bus driver 3 is driven to set a ''1'' which shows that the interruption priority acquisition bus 4 is in use, and the inhibition gate 1 is closed. If a call conflicts, the FF2 is set at the same time and when the following processing becomes abnormal, all FFs are reset. |
