| 摘要 |
Disclosed is a digital signal processing circuit, which can process digital data of at least two different data formats where one word consists of respectively of m and n bits (m and n being positive integers and m>n), for instance 16 and 14 bits, resides in that serial data of the data format where one word consists of m bits (for instance 16 bits) is rearranged into a form conforming to the data format where one word consists of n bits (for instance 14 bits) and that processing (for instance T matrix calculation) is effected according to a bit clock corresponding to the difference in the bit number between m and n, thereby obtaining data conforming to the data format where one word consists of n bits. |
