| 摘要 |
PURPOSE:To realize a high-speed operation of a decimal arithmetic insturction, by performing simultaneously an overflow detection in an arithmetic cycle for a decimal operation using a decimal operator having an arithmetic width of plural bytes. CONSTITUTION:First, the 1st and 2nd operands are set to registers B and A respectively from an instruction decoder 1. At the same time, the valu (''L'') obtained by subtracting 1 from the length of operand to receive an operation is set to an operand length register 2, and the value (''P'') showing the location of the lowest order digit of the operand is set to an operand point register 5. Then ''L'' receives a subtraction by the number of digits that are calculated by a decimal operator 8. An overflow detecting control circuit 12 gives an indication of detection action to an overflow detecting circuit 13 when P>=L is satisfied. Thus a byte Pi [i= P-(L+1)] in an operation output register displaying at overflow is checked in an arithmetic cycle. |
