发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE:To change a writing voltage according to the film thickness of a high resistance layer and the selection of material thereof by providing a conductive layer comprising a barrier layer and a high resistance layer laminated at an emitter window of a bi-polar transistor. CONSTITUTION:An n epitaxial layer 23 is formed on a p<-> type Si substrate 21 through an n<+> buried layer 22 and a p base 25 and an n<+> emitter 27 are selectively formed thereon. A Mo barrier layer 28 is provided on the n<+> layer 27 and a poly Si layer 29 of a high resistance is piled thereon. In addition, utilizing a resist mask 30, Si3N4 mask 31 is formed at the upper portion of the n<+> layer 27. After the removal of the resist 30, the poly Si 29 undergoes a wet type oxidation to selectively form a thick SiO2 32. The Si3N4 31 is etched so as to provide an Al wiring 34. With such an arrangement, the Mo layer 28 checkes Al from punch through to the emitter layer 27 thereby improving the reliability of the device. Moreover, the existence of the Mo 28 enables the greater selection of material and thickness of a high resistance layer thereby allowing te writing voltage to be set in a wider range as desired.
申请公布号 JPS5720463(A) 申请公布日期 1982.02.02
申请号 JP19800095844 申请日期 1980.07.14
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 MIYAMOTO JIYUNICHI
分类号 G11C17/00;G11C17/08;G11C17/16;H01L21/8229;H01L23/525;H01L27/102 主分类号 G11C17/00
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