发明名称 SIGNAL CORRECTING CIRCUIT
摘要 PURPOSE:To facilitate the correction of an error signal by suppressing the redundancy of a data signal by achieving reproduction by substituting a signal, having an occurring error, with a signal of the other channel by utilizing the strong mutual correlation between signals of channel. CONSTITUTION:Signals of two channels from input terminals 1a and 1b are applied to sample holding circuits 3a and 3b via LPFs 2a and 2b to be sampled and held with the control signal of a clock generating circuit 4. Those signals are extracted alternately in time-division mode by a multiplexer 6 under the control of the circuit 4 to be converted an A/D converter 6 into a PCM signal, which is recorded by a recorder 10 via an adder 8 for prescribed data array processing. The recorded signal is inputted to a digital arraying device 11 and a clock generating circuit 12 and if a demultiplexer 15 detects some error, a signal having the error is substituted by the signal of the other channel, which is reproduced to suppress the redundancy of a data signal, thus facilitating the correction of the error signal.
申请公布号 JPS5720048(A) 申请公布日期 1982.02.02
申请号 JP19800094720 申请日期 1980.07.11
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 KATAYAMA YOSHITAKA
分类号 H04L1/00;G11B20/18;H04B1/10;H04B14/04;H04H40/45;H04S1/00 主分类号 H04L1/00
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