| 摘要 |
PURPOSE:To efficiently share a memory without deteriorating a function both systems, by extending an execution cycle of a system whose priority ranking is low, when accessing the memory, and synchronizing both the systems. CONSTITUTION:When a system A accesses a memory 2, signals 14, 13 are outputted from an R/W controlling circuit 8 and a memory selecting circuit 9, synchronizing with the system A side of an execution cycle, and readout and write-in a data 12 through a gate circuit 4 and a data bus ADB. Subsequently, when a system B accesses the memory 2, as soon as the memory 2 is selected by a circuit CSB, a signal READY is outputted to the system B from a synchronization adjusting circuit 10, by which an execution cycle of the system B is extended, and during that time, an address, a data and a control signal are remained in being outputted. As a result, the memory 2 is accessed by the timing of the system B of a clock CLKA, and the data 12 is readout and written in. |
