| 摘要 |
A logic level converter for translating an input signal that swings between first and second voltage levels to an output signal that swings between third and fourth voltage levels. The input signal and its complement are first translated to the desired output levels in a pair of conventional CMOS inverters to produce complementary logic signals. The faster edge of each translated logic signal is used by logic means to control the output signal. Specifically, the leading edge of one logic signal and the trailing edge of the other logic signal are used to control the output signal. The resulting logic level shift circuit provides both fast rise and fall times, and substantially equal propagation delays for both high-to-low and low-to-high signal transitions.
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