| 摘要 |
<p>A circuit arrangement is provided which prevents latching in a power amplifier or supply. A power output transistor drives an inductive load, which is coupled in parallel with the collector-to-emitter path of the transistor. A first diode is coupled between the transistor and a point of reference potential, and is in series with the collector-to-emitter path of the transistor and poled to be of like polarity to the base-emitter junction of the transistor. A capacitor is coupled in parallel with the first diode, and a second diode is coupled in parallel with the inductive load and is poled in an opposite sense to the first diode. The second diode is chosen to have a voltage drop such that a negative voltage impulse from the inductive load will be clipped at a voltage which is the difference between the voltage drops of the first and second diodes.</p> |
