| 摘要 |
PURPOSE:To reduce the process load of a preprocessor, by installing two preprocessors corresponding to each other to a double-series information transmission system. CONSTITUTION:The data received at double-series information transmission devices 1a and 3a are supplied to the 1st preprocessor 11 via the 1st connection signal lines 4a-4c. In the same way, the data received at dobule-series information transmission devices 1b-3b are supplied to the 2nd preprocessor 12 via the 2nd connection signal lines 5b-5f. The data are inspected by these preprocessors 11 and 12, and then double-written into the 1st and 2nd shared memories 13 and 14 only in case the date are verfied normal. In case one of these two series is faulty, only the preprocessor that has read the normal data renews the data of the doubled shared memory 13 or 14. When both systems are normal, the data of same contents are written twice into the shared memories. Then the data of the memories 13 and 14 are transferred through a DMA line to a host CPUs 8 and 9. |
