| 摘要 |
PURPOSE:To surely estimate internal reset signal releasing time by stopping an internal clock of a microcomputer at a prescribed pattern at the time of receiving an external reset active signal from an external reset terminal. CONSTITUTION:An internal clock generating circuit 6 is controlled by an external reset signal S1. Namely when the signal S1 is activated (L level), the circuit 6 fixes internal clocks phi1-phi3 in prescribed patterns, e.g. 'H', 'L', 'L' respectively, and stops them. When the signal S1 is released (turned to 'H'), the circuit 6 generates three-phase internal clocks phi1-phi3 at the time of raising the internal clock phi2 from 'L' to 'H'. Thereby, a tester for testing a LSI can surely grasp the state of the internal clocks at the time of releasing the internal reset signal. |
