| 摘要 |
PURPOSE:To enable an effective TTL-CMOS interface without increasing a chip area, by inserting a constant voltage element between the power source of a CMOS input gate and the source electrode of a P channel transistor. CONSTITUTION:When N channel transistors (Tr) 5, 7, 9, and P channel Tr 6, 8 are connected as illustrated, the voltage level V10 at a connection point 10 is V10=VDDXVTr5, wherein the source gate voltage of the N channel Tr 5 is VTr5. E.g. in a CMOS, LSI used by 5V power source, when VDD=5.0V, V10=3.2-3.5V, and when gm of the P channel Tr 6 and the N channel Tr 7 are equal, a threshold value of an inverter constituted of Tr 5-7 is 1.6-1.75V. Then, this value is reduced to 1.4V a TTL interface level by operating gm of Tr 6, 7. Besides, the input amplitude of an inverter constituted of Tr 8, 9 is improved by 0.8- 1.1V at VIH and by 0.45V at VIL. |
