| 摘要 |
PURPOSE:To increase an operation speed, by compounding an operation result data to a single data by a pair of operators, when a fixed point multiplying instruction is processed, in a digital computer. CONSTITUTION:When a multiplicant and a multiplier are sent out to data buses 41, 40, a data selector 36 continues to select the data bus 41 until the porcuct is derived, and operators 30a, 30b are operated in the same operation mode. When a data of an operation result is sent out to a data bus 42, a data selector 35 or 36 selects a register QR34 or AR33. Also, an operation mode of the operator 30a or 30b is made a mode in which L or R input passes through as it is. As a result, it is sent out to the data bus 42 from the operators 30a, 30b. Since this data has a format which has exchanged upper 16 bits B and lower 16 bits C of the regular product, a correct result is obtained by inputting it to a general register in a register file 20 through a cross-shifter 21. |
