发明名称 BUS FAULT DETECTION SYSTEM OF COMPUTER
摘要 PURPOSE:To detect a faulty place swiftly and efficiently, to easily take proper steps for repairing, and to restore a system swiftly, by detecting whether a bus line is normal or not, in case when a fault has occurred. CONSTITUTION:A CPU is made to execute a check program for writing a data whose all bits are ''0'' and a data whose all bits are ''1'', in an address whose all bits are ''0'' and an address whose all bits are ''1'', respectively, and signals of all bus lines BL in this case are compared with prescribed voltage by a maximum value discriminating circuit A or a minimum value discriminating circuit B, and an output of the deciding circuit A or B, which is caused by a fault of a bus line BL is held by holding circuits 1a, 1b by an output timing of the CPU, and is displayed on a displaying circuit 3. Accordingly, it is also detected that a bus line BL is normal, and it is also known that a faulty place is other than a bus line BL.
申请公布号 JPS5713531(A) 申请公布日期 1982.01.23
申请号 JP19800088199 申请日期 1980.06.27
申请人 MATSUSHITA ELECTRIC WORKS LTD 发明人 NAMIKOSHI YASUMASA
分类号 G06F11/00;G06F11/22;G06F13/00 主分类号 G06F11/00
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