| 摘要 |
<p>PURPOSE:To obtain a decoding circuit which operates stably by achieving correct retiming in either one of some state and a 180 deg. out-of-phase state, by using a signal obtained by decoding an RZ signal which corresponds to an original binary NRZ signal and by frequency-dividing a clock signal. CONSTITUTION:An AND circuit 14 decodes an input biphase signal (a) into an RZ signal which corresponds to an original binary NRZ (Non Return Zero) signal and is obtained by removing the 1st one bit in the succession of ''0''s or ''1''s. Then, an NRZ signal which corresponds to the original binary NRZ signal is obtained by decoding 22 the output of the circuit 14 and a signal obtained by delaying 17 the signal (a) by 1/2T0 (T0=1/f0i where f0 is the bit rate of the original binary NRZ signal) and inverting the delayed signal. On the other hand, a clock signal of a frequency 2f0 extracted from the signal (a) is frequency-divided 23 and a retiming circuit 24 is retimed by the signal f0 to decode the signal (a) without using any synchronizing circuit.</p> |
