| 摘要 |
PURPOSE:To increase a processing speed, by providing a series data of a high speed to a series-parallel converting circuit, converting it to a parallel information to a range within which an FIFO memory is operated, and after that, providing it to the FIFO memory. CONSTITUTION:When a series data of a high speed is inputted to a terminal IN, a shift register 2 outputs a parallel data, and is always monitored by a coinciding circuit 3. At the same time, it is inputted to a register 8, too, is latched, and an output which has been latched is outputted at a speed of 1/8 of the high speed series data, is provided to an FIFO memory 9 of the next stage, and is read. Accordingly, the FIFO memory 9 is able to use that which is operated at a speed of 1/8 of a series data input. |
