| 摘要 |
PURPOSE:To decrease the number of expensive high-speed sample holding circuits, by sampling an input snalog signal through a high-speed sample holding circuit and then sampling the analog signal through plural low-speed sample holding circuits. CONSTITUTION:An input analog signal ei is supplied to a sample holding circuit SH0 that performs a sampling with a sampling pulse train of a sampling period T0. This sampled snalog signal is supplied to, e.g. three sample holding circuits SH1-SH3 to be sampled more to be then applied to A/D converters ADC1-ADC3. For the sample pulse trains to be used by the circuits SH1-SH3, the sample pulse train used in the circuit SH0 is stepped down to a 1/3 frequency from the pulse train that is delayed by an extent longer than the sampling time of the circuit SH0, and furthermore the time is shifted by the period T0. In such way, the circuits SH1-SH3 have the process capacity of a speed much lower than that of the circuit SH0. |
