| 摘要 |
PURPOSE:To realize an individual and high-speed test for an IC for memory, by providing an address generating circuit plus a circuit that compares the read data with an expected data into a memory IC. CONSTITUTION:When a test address signal 404 and an address control signal 400 are applied to an address decoding circuit 3 from a control circuit 1, one of address decoding signals 300-30mO is delivered to select one of memory cell groups iO-in(i=0,1-n). In the case of a writing action, an address signal 102 is delivered to write data 210-21n to be written into the cell groups iO-in. In the case of a reading action, read data 200-20n read out of the groups iO-in plus the signal 102, i.e., an expected value are supplied to a comparator 6. Then the result of coincidence or dissidence is supplied to a data buffer circuit 5 to be delivered by a read data control signal 401 and in the form of a read data 101. |
