| 摘要 |
PURPOSE:To increase the performance of an information processor, by carrying out simultaneously both the read and write processes to the divided different buffer memories and reducing the queuing time of one process due to the other process. CONSTITUTION:A buffer memory 106 is divided into memories A106a and B106b. The data given from a write data register 105 is written into the side of memory B106b in the write W0 and W2, and an address switch circuit B108b provided for selection of address at the side of memory B106b selects and delivers the side of address register B102. On the other hand, the data given from the register 105 is written in the side of memory A106a in the write W1 and W3, and an address switch circuit A108a provided for selection of address at the side of the memory A106a selects and delivers the register B102 side. Thus the memory A106a is read in the write W0 and W2, and the memory B106b is read in the write W1 and W3 respectively. |
