发明名称 Data circuit error and synchronisation failure detector - divides incoming signal by frame for comparison with locally-generated quasi-random sequence
摘要 <p>A special bit sequence, pref. a quasirandom sequence, is sent by the transmitting terminal and generated also in the receiver for comparison with the incoming bit stream and synchronisation with it. The incoming data stream is divided into frames of a specific bit length and the number of errors in each frame detected and the number of consecutive errors are detected. Both are compared with the design criterion for the system to determine whether or not synchronisation has been lost. Measurements of other criteria such as noise and impulse noise are also considered and detected. The method complies with CCITT V52 where a 511 quasi random bit sample is used to determine the transmission quality of a link. Four frames of 128 bits each are used in the comparison method and theoretically the error count should be less than 34. If two frames exceed 34 and two frames are clearly less than 34 frame errors are detected but not a synchronisation error.</p>
申请公布号 DE3023860(A1) 申请公布日期 1982.01.21
申请号 DE19803023860 申请日期 1980.06.26
申请人 LICENTIA PATENT-VERWALTUNGS-GMBH 发明人 EICHLER,PETER,ING.
分类号 H04L7/00;H04L7/04;(IPC1-7):04L7/04 主分类号 H04L7/00
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