| 摘要 |
PURPOSE:To reduce the circuit components, by commonly using an address selector with a plurality of memories, and making the selection of memories only with a memory switch. CONSTITUTION:In case of a write-in mode, W, a mode switch 6 instructs the write- in mode to memories 11A-11N and a selector 8 with a switching signal R/W. Further, at first, the selector 8 selects the memory 11A with a chip selection signal CS, then an address selector 10 renews the address value with a clock signal CK and an input data Di is written in the memory 11A every time. Next, in case of a readout mode R, the switch6 instructs the readout mode to the memories 11A-11N and the selector 8 with the signal R/W. Further, since the selector 8 selects all the memories of 11A-11N, the address value of the selector 10 is sequentially renewed with the clock signal CK and output data D0(1)-D0(N) are read out in parallel from the memories every time. |
