Magnetic core memory inhibit current driver circuit

摘要

A low cost, low power inhibit current drive circuit includes a pair of sense-inhibit conductors each inductively coupling 16K low drive memory cores and having sufficiently low resistance to permit steady state inhibit current magnitudes to be energized by a 5 volt source which is diode coupled thereto, a switch coupled to selectively pass inhibit current in response to a command signal, a storage capacitor coupled to the transistor collector, and a series combination of an inductor and a resistor coupled to charge the capacitor to a voltage greater than 5 volts and thus provide a rapid rise of inhibit current to the steady state level upon closure of the switch. Use of the charged capacitor to provide high voltage energy at switch closure reduces the required maximum current from the high voltage source while the inductor reduces capacitor charging time for a given size of series resistor to further reduce the maximum current requirement from the high voltage source.