| 摘要 |
PURPOSE:To shorten an access time by accessing a memory chip with a paqe-mode accessing function in page mode and by accessing another chip while column addresses are changed over by one chip. CONSTITUTION:A row address RAS is sent out to an address line 70 and when a row address line 100 falls, each chip latches the row address at the same time. Then, the column address of data in a memory chip 60 is sent to the line 70 and when the column address line of the chip 60 falls, the chip 60 latches the column address. Further, the column address of data in a chip 61 is sent to the line 70 and when a line 111 falls, the chip 61 latches the column address. Data read out of both the chips are alternated by an AND gate 130 with their selection signals 120 and 121 and sent to a readout line 90. |
