| 摘要 |
PURPOSE:To decrease a minimum magnetization inversion interval and the extent of a limit phase shift as much as possible by reducing the number of bits of a logic [0] in succession as much as possible by reducing the number of continuous [0]s in terms of probability. CONSTITUTION:The result of AND between pulses reproduced from an odd-numbered track and an even-numbered track following it is applied to corresponding to NRZI demodulators 31-38. Words having bits inverted in logic by a recording data processor, i.e. the outputs of the NRZI demodulators 32, 34, 36, and 38 among the demodulators 31-38 are supplied to inverters 52, 54, 56, and 58, which restore each bit to its original logic. Thus, each word inputted to a speed converting circuit 7 is rearranged in the word order when an ADC2 is outputted and a decoder circuit 8 checks and corrects an error, so that a DAC9 converts the input into the original audio signal. |
