发明名称 MEMORY CONTROLLER
摘要 PURPOSE:To shorten a readout time by selecting a readout start signal from a timing control circuit according to whether an error is detected or not in readout data, and by outputting it to a readout data register. CONSTITUTION:When data 101 read out of a storage device 1 has no error, the access time of data readout operation is only the sum of a data readout time regarding the storage time 1 and the time when the readout data 101 propagates in an error bit correcting circuit 23, thereby shortening the memory access time. If the data 101 has an error, a signal selecting circuit 33 masks the 1st readout data latch signal 105a outputted from a timing control circuit 32 and selects a readout data latch signal 105b to send it to a readout data register 31.
申请公布号 JPS578999(A) 申请公布日期 1982.01.18
申请号 JP19800083263 申请日期 1980.06.19
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 HIRAOKA TAKASHI
分类号 G06F11/10;G06F12/16 主分类号 G06F11/10
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