| 摘要 |
PURPOSE:To shorten the required time of control which corresponds to sequential instructions, by determining substantially an address for fetching a new instruction at the point in time when the sequential instructions are executed and the execution is completed. CONSTITUTION:Instructions, when read out from a storage device, are set in instruction buffer register 7-1-7-3 in sequence. On the other hand, instructions are supplied from the register 7-1 to a processing part 9 via a selector circuit 8 as the processing of a pipeline processing part 9 progrsses. For example, if instructions at positions I0-I4 in the figure are supplied to the processing part 9 and the execution is finished, only the next sequence instruction pointer NSiP5 has a logic 1. When instructions are prefetched, a register 7-3 is empty and if the pointer NSiP5 indicates a logic 1, pseudo-sequential instructions still remain in the register 7-2, determining a value for correcting the contents of an instruction address register. Consequently, the required address is determined and set in an effective address register. |
