| 摘要 |
PURPOSE:To secure the display of the clock fault with every package for the user by providing the detection circuit to confirm the normalcy of the clock plus the circuit to give the test to the operation of the detection circuit to each logic circuit package of the information processor. CONSTITUTION:With supply of the clock of cycle T to the clock detection circuit provided in each logic package of the information processor, T1<T2<T<T3<T1+ T is secured when the delay time is referred to as T1, T2 and T3 for terminals C1, C2 and C3 each of delay circuit D1. And the output of logic gates G1-G3 caused by the output of FF (A, B) are all 0 if the clock is supplied along with the output of gate G4 featuring also 0. Thus no fault occurring is shown. If the clock is fixed to 0 or 1 due to occurrence of the fault, output ''1'' is delivered through gate G4 to display the fault occurrence. And at the same time, the test circuit selects 1 or 0 as the test data in case the test is given to the clock detection circuit and then supplies it to the clock detection circuit. |
