发明名称 FREQUENCY DIVIDING CIRCUIT
摘要 PURPOSE:To obtain an odd-numbered frequency-division ratio of an E tone, etc., by providing an asynchronous counter and a shift register and by noticing that even when a signal whose 0.5 pulse component is disregarded, namely, below a 50% duty cycle exactly is used, no aural influence is exerted. CONSTITUTION:To obtain an E tone, a master clock signal is frequency divided by 379. Preset data 187 of the E tone is set to terminals P1-P8 of counters 101-108. A master clock signal inputted from an input terminal 1 is frequency-divided by counters 101-108 and when the 188th pulse exceeding the preset data is applied, a coincidence signal (j) is obtained from an AND circuit 12. This signal is inputted to shift registers 111 and 112 and when an output k1 at a terminal Q11 is high, a load signal o1 is generated to lead the preset data out from terminals Q1-Q8, so that the counters 101-108 are reset and restart counting.
申请公布号 JPS577634(A) 申请公布日期 1982.01.14
申请号 JP19800081041 申请日期 1980.06.16
申请人 VICTOR COMPANY OF JAPAN 发明人 SHIROMIZU TAKAMI
分类号 G10H5/00;H03K21/00;H03K23/00;H03K23/58;H03K23/64;H03K23/66 主分类号 G10H5/00
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