| 摘要 |
PURPOSE:To obtain high withstand voltage even if surface concentration of a well and a n layer being low set and increase current per unit gate by means of channel length reduction, by forming both channels in complementary-type FETs by double diffusion and determining both the threshold values according to the concentration of the channel layers. CONSTITUTION:A P well 2 is formed in a N type substrate 1, and then a N type channel layer 3 and a P type source layer 4 are formed through the same window. A P type drain layer 4' is formed inside said well 2, and the surface is equipped with electrodes 6, 15, and 16 by opening a gate oxidizing film 5, a field oxidizing film 13, and an insulating film 14, so that a Pch FET is formed. Similarly, a N layer 8 is formed in a P well 7, and then a P type channel layer 9 and a N type source layer 10 are formed by double diffusion through the same window, so that a Nch FET is formed. Manufacture of channels in both FETs by double diffusion allows their threshold values to be determined according to the concentration of the diffusion layers serving as channels. Even if the surface concentration of the P well and the N layer is low set, the depletion layer expands in a direction opposite to the channel. Therefore, withstand voltage can be prevented from being lowered due to punchthrough and avalanche breakdown caused by low surface concentration, so that high withstand voltage can be obtained. |
