| 摘要 |
PURPOSE:To enable high-speed processing, by converting a pure binary number into a binary coded decimal with a simplified processor. CONSTITUTION:A pure binary number to be converted is set to a P of a shift register 10 and the number of bits in a pure binary number to be set is set to a monitor circuit 16. The shift register 10 is shifted left by one bit every output of a controller 18 having a 3-bit counter. In this case, ''0'' is inserted to the least significant bit. Next, one block Q0 out of a column Q is selected in a multiplexer 11, based on a 3-bit counter of the controller 18, the content of the block Q0 is compared with 5(=0101) with a comparator 13, and if the result is more than the value, a YES signal is applied to a gate 14. On the other hand, 3 is added to the block Q0 with an adder 12, and the signal output and one of an output not added with 3 are applied to the gate circuit 14 and the result is selected with the YES signal being the output signal of the comparator 13. |
