| 摘要 |
PURPOSE:To reduce converting speed, by changing a comparison time depending on the difference between analog input and output of a DA converter. CONSTITUTION:To a sequential comparison type AD converter consisting of a DA converter 1, comparator 2, sequential comparison regiser 3, analog input terminal 4, start pulse input terminal 5, and control clock terminal 6, a control clock control circuit consisting of a comparator 8, D flip-flop 9 and OR gate 10 is added. In the comparator 8, an input analog voltage and an output of the DA converter 1 are compared, and if the difference is smaller than a certain threshold value, a control clock on-time is made longer to prevent mis-code. If the difference is greater than the threshold value, since no mis-code is produced, the on-time of the control clock can be made shorter. |
