发明名称 |
Logical waveform generator |
摘要 |
Input logical data is sequentially divided by a data dividing circuit for each time slot into n data trains, of which each data block has an n time slot length. A clock signal which can be arbitrarily timed, is divided by a clock dividing circuit into a n clock signals which are displaced one time slot apart in phase and which occur with a period of n time slots. In a logical circuit, the divided clock signals are controlled by the divided data trains corresponding thereto, and the controlled clock signals are time multiplexed by a multiplexing circuit, whereby output data with which the input logical data has been timed by the clock signal is obtained.
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申请公布号 |
US4310802(A) |
申请公布日期 |
1982.01.12 |
申请号 |
US19790069348 |
申请日期 |
1979.08.24 |
申请人 |
NIPPON TELEGRAPH & TELEPHONE PUBLIC CORP. |
发明人 |
ICHIMIYA, YOSHICHIKA;SUDO, TSUNETA;MARUYAMA, HIROMI;SUGAMORI, SHIGERU;SUMIDA, SUSUMU;TOKUNO, TAKASHI |
分类号 |
G06F11/22;G01R31/3183;G01R31/319;G06F1/06;H03K5/135;H03K5/156;(IPC1-7):H03K5/22 |
主分类号 |
G06F11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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