| 摘要 |
PURPOSE:To perform the pipeline operation smoothly, by completing decoding of a write address to an RAM in the preceding micro cycle and by writing data to the RAM immediately at the start of the current cycle. CONSTITUTION:One of signals 8c settled in the first micro cycle sends one of signals 8d, which became a write signal by a clock 8a and a write clock gate group 81, to a memory cell 56. Though writing is completed by this operation, R3 and R4 are read out from RAMs 50 and 51 respectively similarly to the first micro cycle in the processing (R3+R4 R5) where the operation is started from this cycle. |
