| 摘要 |
PURPOSE:To reduce the amount of hardware required for discriminating whether retry is permitted or not, by providing one counter for the whole of a CPU. CONSTITUTION:When a fault is detected somewhere, ''1'' is given to an OR signal 11 of the fault detection signal from each part of a CPU, and the output of respective timing pulses is suppressed in gates 120-12N-1. A counter 13 generates N different values successively for respective inputs of N phase timing pulses and is returned to the original value after clapse of one machine cycle. Consequently, the value of this counter 13 is read to detect the progress of the output of N phase timing pulses. |
