发明名称 MEMORY CONTROL METHOD
摘要 PURPOSE:To achieve high-speed data transfer and processing, by making a memory dual and by providing data and address busses of two systems and a circuit which switches dual memories to busses of two systems and controls them. CONSTITUTION:Data is written from a high-speed data source 4 to a memory 2 through a switch 6, and meanwhile, a microprocessor MPU3 reads data of a memory 1 through a switch 7 and processes it. When data read and data input are completed, a switch control 8 is started by the control of the MPU3, and switches 6and 7 are switched to the contact (a) side. Then, the memory 2 is connected to an address bus 10 through the switch 7, and the memory 1 is connected to a data bus 9 through the switch 6. Consequently, data is read out from one memory while data is written to the other memory, and busses are switched when a series of this control is completed. This operation is repeated in a high speed.
申请公布号 JPS573161(A) 申请公布日期 1982.01.08
申请号 JP19800075553 申请日期 1980.06.06
申请人 HITACHI LTD 发明人 TERAJIMA HISANORI
分类号 G06F12/16;G06F5/16;G06F13/00 主分类号 G06F12/16
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