发明名称 Delay lock loop modulator and demodulator
摘要 A delay lock loop has a fixed delay element, means for detecting the edge transitions of pulses, analog or digital feedback means related to the timing differences between the edge transitions of a pair of pulses and a variable delay means responsive to the feedback means for adjusting the timing differences between a pair of pulses in response to the feedback signals. In the analog embodiment, the feedback may be a voltage related feedback with a varying voltage controlling a voltage responsive variable delay means. In the digital embodiment, the feedback means may use a counter responsive to signals from an edge detecting flip-flop and the counter may control a programmable delay means.
申请公布号 US4309673(A) 申请公布日期 1982.01.05
申请号 US19800129056 申请日期 1980.03.10
申请人 CONTROL DATA CORPORATION 发明人 NORBERG, GAYLE R.;PETRICH, DENNIS M.
分类号 H03K5/135;G06F1/04;H03L7/00;H04L7/033;(IPC1-7):H03C3/00;H03D3/00 主分类号 H03K5/135
代理机构 代理人
主权项
地址