发明名称 PROCESSING CIRCUIT FOR DIGITAL SET VALUE
摘要 PURPOSE:To allow only one selected condition circuit to obtain a digital input by setting the output level of only the selected condition circuit to zero and by holding output sides of the other unselected condition circuit and a setting circuit at high levels. CONSTITUTION:If a CPU1 supplies a three-digit digital value to a setting circuit 11, this output is supplied as a positive high-level signal to respective condition circuits A, B, C, D, E, and F in common. Then, when a changeover decoder 12 is not in operation, every condition circuit is held at a positive high level and, therefore, generates no set value signal regardless of the existence of the outputting of the set value signal. When the decoder 12 selects one of the condition circuits, the output level of the selected condition circuit is zero through-out a selection time and the set value signal is the output of the condition circuit. Thus, only one selected condition circuit obtains a digital input.
申请公布号 JPS57704(A) 申请公布日期 1982.01.05
申请号 JP19800074193 申请日期 1980.06.04
申请人 YAMATAKE HONEYWELL CO LTD 发明人 IMAI RIYOUZOU
分类号 G06F3/023;G05B15/02 主分类号 G06F3/023
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